The Tektronix DG2020 is a high-performance 200 Mb/s digital pattern generator designed for characterization, debugging, and testing of digital systems. Featuring a modular architecture supporting up to 36 channels with selectable output pods, the DG2020 provides flexible data rate controls, deep pattern memory, and extensive sequencing capabilities.
Specifications
General
| Parameter | Value |
|---|---|
| Interfaces | GPIB (IEEE-488.2), RS-232-C |
| Display | 6.4-inch color TFT LCD |
| Warm-Up Time | 20 minutes |
Physical
| Parameter | Value |
|---|---|
| Power Supply | 90 to 250 V AC, 48 to 63 Hz, 300 W max |
| Operating Temperature | 10 to 40 °C |
| Dimensions (W×H×D) | 362 mm × 164 mm × 492 mm |
| Weight | 10.5 |
Output Channels & Signal Format
| Parameter | Value |
|---|---|
| Number of Data Channels | Up to 36 channels (12 channels per pod, up to 3 pods) |
| Output Pod Options | P3410 (TTL), P3420 (ECL), P3447 (Variable Voltage) |
| Data Output Format | NRZ (Non-Return-to-Zero) |
| Output Impedance | 50 Ω |
Timing & Clocking
| Parameter | Value |
|---|---|
| Maximum Data Rate | 200 Mb/s |
| Clock Frequency Range | 0.1 Hz to 200 MHz |
| Clock Frequency Resolution | 4 digits |
| Internal Clock Accuracy | ±100 ppm |
| Clock Source Options | Internal, External |
Output Voltage Levels
| Parameter | Value |
|---|---|
| P3447 High-Level Output Range | -2.0 V to +7.0 V |
| P3447 Low-Level Output Range | -3.0 V to +6.0 V |
| P3447 Voltage Amplitude Range | 0.1 Vp-p to 9.0 Vp-p (into 50 Ω) |
| P3447 Voltage Level Resolution | 10 mV |
Pattern Memory & Sequencing
| Parameter | Value |
|---|---|
| Pattern Memory Depth | 64 K words per channel (64,000 words) |
| Block Size | 8 words |
| Sequencer Loop Count Range | 1 to 65,536 (or infinite) |
| Maximum Sequence Steps | 4,000 steps |
| Maximum Subroutines | 128 |
Trigger & Synchronization
| Parameter | Value |
|---|---|
| Trigger Modes | Auto, Normal, Single |
| Trigger Sources | Internal, External, Manual |
| External Trigger Input Level | -5.0 V to +5.0 V |
| Sync Output Type | 1 channel, TTL level |
System Interfaces & Storage
| Parameter | Value |
|---|---|
| Removable Storage Media | 3.5-inch floppy disk drive (1.44 MB, MS-DOS format) |
Software & Control
| Parameter | Value |
|---|---|
| Programming Language Compatibility | SCPI-compatible |
Environmental & Safety
| Parameter | Value |
|---|---|
| Storage Temperature Range | -20 °C to +60 °C |
| Operating Humidity Range | 20% to 80% RH (non-condensing) |
| Operating Altitude | Up to 4,500 m |
Delay / Phase Control
| Parameter | Value |
|---|---|
| Clock Delay Range | 0 ns to 20.00 ns |
| Clock Delay Resolution | 10 ps |
External Clock Input
| Parameter | Value |
|---|---|
| External Clock Input Frequency Range | DC to 200 MHz |
| External Clock Input Impedance | 50 ohms |
| External Clock Input Amplitude | 0.4 Vp-p to 5.0 Vp-p |
P3410 Output Pod
| Parameter | Value |
|---|---|
| P3410 Channel Count | 12 channels |
| P3410 High-Level Output Voltage | >= 4.4 V (into 1 Mohm), >= 2.2 V (into 50 ohms) |
| P3410 Low-Level Output Voltage | <= 0.1 V (into 1 Mohm or 50 ohms) |
| P3410 Output Impedance | 50 ohms |
| P3410 Rise/Fall Time | <= 1.5 ns (into 1 Mohm, 10 pF) |
P3420 Output Pod
| Parameter | Value |
|---|---|
| P3420 Channel Count | 12 channels |
| P3420 Voltage Level Range | -2.0 V to +7.0 V (into 1 Mohm) |
| P3420 Output Voltage Resolution | 10 mV (into 1 Mohm) |
| P3420 Output Impedance | 50 ohms |
| P3420 Voltage Amplitude Range | 0.5 V to 9.0 V (into 1 MΩ) |
| P3420 Rise/Fall Time | ≤ 1.5 ns (into 50 Ω, 1.0 V to 3.0 V swing) |
Trigger Input
| Parameter | Value |
|---|---|
| Trigger Input Impedance | 1 Mohm |
| Minimum Trigger Pulse Width | 10 ns |
Power Requirements
| Parameter | Value |
|---|---|
| Power Consumption | 300 W maximum |
| Input AC Voltage Range | 90 V to 250 V AC |
| Line Frequency Range | 48 Hz to 63 Hz |
Pattern Generation & Memory
| Parameter | Value |
|---|---|
| Maximum Pattern Blocks | 256 |
Inputs & Outputs
| Parameter | Value |
|---|---|
| Event Input Connector Type | BNC (rear panel) |
| Event Input Impedance | 1 kΩ |
| Event Input Level | TTL compatible |
| Event Input Minimum Pulse Width | 30 ns |
| Event Input to Sync Output Delay | ≤ 60 ns + 1.5 clock cycles |
| Clock Output Connector Type | BNC (rear panel) |
| Clock Output Level | ECL level (into 50 Ω) |
Compliance & Safety
| Parameter | Value |
|---|---|
| Safety Standards | UL3111-1, CSA1010.1, EN61010-1 |
| EMC Standards | EN55011, EN50082-1, FCC Part 15 Class A |
Technology
Digital Pattern Generation
Applications
Digital circuit characterization, semiconductor testing, and bus emulation