State vs. Timing Analysis in Logic Analyzers

Timing analysis samples signal levels at uniform intervals determined by the logic analyzer's internal clock. Because this sampling occurs independently of the target system's clock, it is ideal for measuring physical-layer timing parameters, signal transitions, and propagation delays. This mode behaves similarly to a digital oscilloscope with a single-bit vertical resolution, showing when edges transition relative to the instrument's timebase.

To capture rapid signal transitions or narrow glitches, timing analyzers must sample significantly faster than the system clock speed. For example, the Keysight 16950A provides timing acquisition up to 1.2 GHz on half-channel configurations (and 600 MHz on full channels). It also features a 4 GHz (250 ps) high-resolution timing zoom with a 64K sample depth to isolate brief transients. Similarly, the Keysight 16717A conventional timing mode runs up to 667 MHz on half channels and incorporates a fixed 2 GHz high-resolution timing zoom.

State analysis uses an external clock supplied by the device under test to trigger sampling. This external clock defines when data is valid, such as on the rising edge of a system clock or memory strobe. Instead of plotting continuous time history, state analysis records the sequence of logic states as they occur. It ignores all signal activity between active clock edges, saving memory and focusing purely on the functional logic flow of the system.

Because state mode matches the clocking of the target hardware, the logic analyzer's maximum supported state clock rate must equal or exceed the speed of the bus under test. The Keysight 16717A module supports a maximum state clock speed of 333 MHz with a 333 Mb/s state data rate. For higher-speed systems, the Keysight 16950A supports a state clock rate of up to 600 MHz and a maximum state data rate of 800 Mb/s.

Instruments configured for state mode require physical access to system clock and qualifier signals. For high-density systems, modules like the Tektronix TLA7BB4 provide 136 total input channels, which include 4 dedicated clock channels and 4 dedicated qualifier channels to simplify synchronous bus connections.

The decision to use state or timing analysis depends on your specific troubleshooting goals.

When to Use Timing Analysis:

• You need to measure physical margins such as setup and hold times.
• You suspect asynchronous anomalies like glitches, crosstalk, or incorrect propagation delays.
• Your device under test does not export a reliable, synchronous clock signal.

When to Use State Analysis:

• You need to trace software execution, instructions, or packet-level data across an address or data bus.
• You must monitor system activity over extended periods; state analysis uses memory more efficiently because it only saves data on valid clock transitions.
• You are verifying protocol compliance on parallel buses (e.g., DDR memory interfaces).