The Keysight Technologies (formerly Agilent) 16760A is a high-performance 34-channel state and timing logic analyzer module designed for the 16700 series logic analysis systems. Engineered for high-speed digital buses, it offers differential input support (compatible with LVDS, HSTL, and SSTL), state analysis data rates up to 1.5 Gb/s, and a massive standard acquisition memory of 64 M samples (scalable to 128 M samples in 1.5 Gb/s mode). A standout feature of the 16760A is its innovative Eye Scan technology, which allows simultaneous eye diagram rendering across all channels without moving probes, complemented by an automatic Eye Finder timing adjustment with 10 ps resolution.
Specifications
General
| Parameter | Value |
|---|---|
| Interfaces | Agilent/HP 16700 series backplane interface |
| Display | None (uses mainframe display) |
Physical
| Parameter | Value |
|---|---|
| Power Supply | Powered by mainframe backplane |
| Operating Temperature | 0 to 50 °C |
Acquisition and Channels
| Parameter | Value |
|---|---|
| Number of Channels | 34 channels per module |
| Maximum Data Rate | 1.5 Gb/s |
| Maximum State Clock Speed | 800 MHz |
| Eye Finder Resolution | 10 ps |
Memory and Record Length
| Parameter | Value |
|---|---|
| Standard Memory Depth | 1 M samples |
| Maximum Memory Depth (1.5 Gb/s Mode) | 128 M samples |
Input Signal Characteristics
| Parameter | Value |
|---|---|
| Input Configurations | Differential and single-ended |
| Supported Signal Formats | LVDS, HSTL, SSTL, and other high-speed differential/single-ended signals |
Features
| Parameter | Value |
|---|---|
| Eye Scan Feature | Simultaneous eye diagram analysis across hundreds of channels without probe movement |
Mainframe Compatibility and Electrical Power
| Parameter | Value |
|---|---|
| Compatible Mainframes | Agilent/Keysight 16700 series (including 16700A, 16700B, 16702A, 16702B) |
| Backplane Slot Width Requirements | 1 slot (single-slot module) |
Electrical Inputs
| Parameter | Value |
|---|---|
| Minimum Input Voltage Swing (Single-Ended) | 200 mV p-p |
| Minimum Input Voltage Swing (Differential) | 100 mV p-p |
| Input Threshold Range | -3.0 V to +5.0 V |
| Input Threshold Resolution | 10 mV |
Performance
| Parameter | Value |
|---|---|
| Setup and Hold Window | 330 ps |
Triggering
| Parameter | Value |
|---|---|
| Number of Trigger Levels | 12 |
| Trigger Pattern Terms | 8 |
| Trigger Range Terms | 2 |
| Trigger Edge Terms | 2 |
| Trigger Timer Terms | 2 |
Technology
Logic Analysis
Applications
High-speed digital bus analysis, timing and state validation, and eye diagram signal integrity testing