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N4901B

Keysight Technologies (Agilent HP)BERT, Error Analyzers

The Keysight (Agilent) N4901B Serial BERT 13.5 Gb/s is an industry-leading bit error rate tester designed for high-performance serial bus characterization, transceiver testing, and semiconductor validation. Supporting data rates from 150 Mb/s to 13.5 Gb/s, the N4901B features integrated clock data recovery (CDR), advanced jitter injection capabilities, true differential inputs/outputs, and a comprehensive analysis measurement suite.

BERTReceiver TestingSerial Data AnalysisSignal Integrity

Specifications

General

ParameterValue
InterfacesGPIB, LAN, USB, VGA
Display8.4-inch color LCD touch screen

Physical

ParameterValue
Power Supply100 to 240 V AC, 50 to 60 Hz
Operating Temperature5 °C to 40 °C
Dimensions (W×H×D)424 mm x 222 mm x 570 mm

System Architecture and Key Performance

ParameterValue
Minimum Data Rate150 Mb/s
Maximum Data Rate13.5 Gb/s
Upgrade CapabilitiesUpgradeable from 7 Gb/s to 13.5 Gb/s
Operating ModesPattern Generator, Error Detector
Chassis ConfigurationIntegrated Mainframe

Pattern Generator (TX) Specifications

ParameterValue
Output Data Rate Range150 Mb/s to 13.5 Gb/s
Output Transition Time (10% to 90%)< 25 ps (20% to 80%)
Output Intrinsic Jitter< 1 ps RMS (typical)
Output Amplitude Range0.1 V to 1.8 Vp-p (single-ended), 0.2 V to 3.6 Vp-p (differential)

Error Detector (RX) Specifications

ParameterValue
Input Data Rate Range150 Mb/s to 13.5 Gb/s
Input Sensitivity (Differential)< 50 mV pp
Input Interface TypeTrue differential inputs

Clocking and Clock Recovery

ParameterValue
Integrated CDR Range 11.05 Gb/s to 1.6 Gb/s
Integrated CDR Range 22.11 Gb/s to 3.20 Gb/s
Integrated CDR Range 34.23 Gb/s to 6.40 Gb/s
Integrated CDR Range 49.9 Gb/s to 10.9 Gb/s

Jitter Injection and Tolerance

ParameterValue
Jitter Modulation Range200 ps
Jitter Modulation Frequency RangeDC to 1 GHz

Analysis and Software Features

ParameterValue
Operating SystemWindows XP
Measurement Suite CapabilitiesBathtub curve, output level, Q-factor, spectral jitter decomposition, fast eye mask, error location capture

Pattern Generator

ParameterValue
PRBS Patterns2^7-1, 2^10-1, 2^11-1, 2^15-1, 2^23-1, 2^31-1
User Pattern Memory1 bit to 32,768,000 bits
PG Delay Control Range-750 ps to +750 ps
Output Crossing Point Adjustment Range20% to 80%

Clock and Delay

ParameterValue
Clock Output Frequency Range150 MHz to 13.5 GHz (option-dependent)
Clock Output Amplitude Range0.1 Vp-p to 2.0 Vp-p (single-ended)
Sub-rate Clock Divider Ratios2, 4, 8, 16

Error Detector

ParameterValue
Error Detector Input Impedance50 Ω (nominal)
Error Detector Input Voltage Range-2.0 V to +3.0 V

Environmental

ParameterValue
Storage Temperature Range-40 °C to +70 °C

Generator Parameters

ParameterValue
PG Output Offset Range-2.00 V to +3.00 V
PG Output Termination Voltage Range-2.00 V to +3.00 V
PG Output Transition Time (20% to 80%)< 25 ps (20 ps typical)
PG Clock Output Offset Range-2.00 V to +3.00 V
PG External Clock Input Frequency150 MHz to 13.5 GHz
PG External Clock Input Amplitude200 mVpp to 2.0 Vpp

Analyzer Parameters

ParameterValue
ED Clock Input Frequency Range150 MHz to 13.5 GHz
ED Data Input Threshold Range-2.00 V to +3.00 V
ED Data Input Threshold Resolution1 mV
ED Clock-to-Data Delay Resolution100 fs
ED Auto-align CapabilitiesThreshold and phase auto-alignment

Error Insertion

ParameterValue
Error Insertion Rate Range1.0 × 10^-2 to 1.0 × 10^-9

Sync & Trigger

ParameterValue
Pattern Sync Output Amplitude1 V nominal into 50 Ω
Trigger Output Amplitude1 V nominal into 50 Ω

Technology

Bit Error Rate Testing (BERT)

Applications

High-speed digital transceiver characterization, semiconductor design validation, telecom/datacom system testing